1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to techniques for manufacturing integrated circuit memory devices based on floating gate memory cells having dual floating gate oxide structures.
2. Description of Related Art
Floating gate transistors are the basis of a number of integrated circuit memory devices, including flash memory. In flash memory design, improvements are being made in floating gate transistor design to allow lower voltage operation, larger memory arrays, and improved endurance and charge retention of the memory cells.
One floating gate transistor design described by Hisamune, et al., "A High Capacitive-Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories," IEDM 1993, pp. 19-22, involves the use of a so-called dual thickness gate oxide structure. According to the Hisamune, et al. structure, the oxide between the semiconductor substrate and the floating gate of a floating gate cell has a thicker region over the moderately doped channel, and a thinner tunnel region on the sides of the channel adjacent to source and drain. This has the effect of increasing the capacitive-coupling ratio of the cell, allowing lower voltage operation of the flash memory cells.
The capacitive-coupling ratio is defined by the quotient of the capacitance of the inter-poly dielectric between the control gate and the floating gate, and the total capacitance of the floating gate structure between the control gate and the source and drain regions. By reducing the total capacitance of the floating gate and increasing the capacitance between the floating gate and the control gate, using the dual thickness gate oxide, the capacitive-coupling ratio is increased. A higher capacitive-coupling ratio allows lower voltage operation, because a greater proportion of the voltage applied to the control gate of the floating gate cell is transferred to the floating gate. Higher voltage on the floating gate increases the electric field across the floating gate regions of the tunnel oxide, and thereby increases the efficiency of the tunneling operations used for programming and/or erasing the array.
Although the Hisamune, et al. structure is suitable for establishing low voltage operation on flash memory devices, the design does not address critical problems with prior art floating gate cells in general. In particular, charge retention and endurance of floating gate cells are limited by so-called band-to-band tunneling current and hot hole injection current, which occur between the floating gate and the source, drain and/or substrate of the transistor. According to the Hisamune, et al. structure, and other prior art structures, sufficient control of the band-to-band tunneling current has not been achieved. In Hisamune, et al., for example, the tunnel oxide quality and thickness uniformity in the dual thickness gate oxide structure proposed are difficult to control. Without control of the quality of the oxide, and other parameters in the manufacturing process, band-to-band tunneling current and hot hole injection are not adequately controlled, and the endurance and charge retention characteristics of the device suffer.
Accordingly, it is desirable to provide an improved manufacturing process and design for a floating gate transistor having a dual thickness floating gate oxide.